To connect chips in an integrated circuit chip or board and chips mounted on different boards, various high speed interfaces are used widely. Examples of such high speed interfaces include Serial-ATA (Advanced Technology Attachment), PCI (Peripheral Component Interconnect)—Express, USB3.0 and 10 Gbit-Ethernet (registered trademark).
A receiving device provided in a high speed interface as described above may have a function to shape the waveform of a received signal which is deteriorated due to attenuation in a transmission path. The function to shape the waveform is achieved by disposing a digital equalizer in a subsequent stage of an analog/digital converting part, or by passing an analog signal which is input via a transmission path to an adaptive equalizer (see, for example, Japanese National Publication of International Patent Application No. 2005-517325 and Japanese Laid-open Patent Publication No. 2007-325263).
FIG. 28 illustrates an example of a conventional receiving device having an adaptive equalizer. Further, FIG. 29 illustrates a diagram describing altering processing in a conventional adaptive equalizer.
In the receiving device having the conventional adaptive equalizer, a high frequency component of an input signal in which the high frequency component has attenuated in the process of passing through a transmission path is emphasized by an adaptive equalizer (equalizer) 401. By this emphasizing operation, the waveform of the input signal is corrected. This corrected signal is input to a CDR (clock and data recovery) circuit 402 and an ADC (analog digital converter) 403. The CDR circuit 402 alters a phase relation between the input signal received via the equalizer 401 and an internal clock of the receiving device. Thus, a clock signal indicating determination timing for determining a logical value of received data is obtained. Further, based on this clock signal, received data containing a correctly determined logical value is output. On the other hand, the ADC 403 samples and quantizes an output of the equalizer 401 in synchronization with the above-described clock signal, and passes the quantization result to a dispersion calculating circuit 404. This dispersion calculating circuit 404 counts the quantization result received from the ADC 403. From a result of this counting, a distribution of signal levels as illustrated in FIG. 29 is obtained. The dispersion calculating circuit 404 calculates a dispersion value with respect to this distribution. Based on the obtained dispersion value, an equalizer coefficient set to the equalizer 401 is controlled. Note that the equalizer coefficient will be abbreviated to EQ coefficient in the following description. For example, the dispersion calculating circuit 404 monitors a change in the above-described dispersion value while varying the EQ coefficient in response to a start signal from a controlling unit, so as to search for the EQ coefficient with which the dispersion value becomes minimum. Completion of this search is notified to the controlling unit by an end flag. After completion of the search, the optimum EQ coefficient found by the search is set fixedly to the equalizer 401. In this way, the amount of the high frequency signal emphasized by the equalizer 401 is altered optimally (Japanese Laid-open Patent Publication No. 06-103696).
Now, in the above-described conventional receiving device, an output voltage value of the equalizer 401 is converted into digital data of a plurality of bits. For this conversion, the ADC 403 having a plurality of comparators is provided in the receiving device. To the comparators provided in the ADC 403, the output of the equalizer 401 and the clock signal generated in the CDR circuit 402 are distributed. Accordingly, for the purpose of ensuring a necessary current amount, a buffer is provided in the conventional receiving device. Further, in the dispersion calculating circuit 404, a complicated calculation circuit is provided for counting the distribution of signal levels and calculating the dispersion thereof. Thus, in the conventional receiving device, numerous comparators, buffers, and calculation circuits are provided for control of the EQ coefficient set to the adaptive equalizer. Large power is consumed by these comparators and calculation circuits.